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Data Sheet July 2000
LU6612 FASTCAT TM Single-FET for 10Base-T/100Base-TX
Features
10 Mbits/s Transceiver
s
General
s
Compatible with IEEE * 802.3u 10Base-T standard for twisted-pair cable Autopolarity detection and correction
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Autonegotiation (IEEE 802.3u clause 28): -- Fast link pulse (FLP) burst generator -- Arbitration function -- Accepts preamble suppression -- Operates up to 12.5 MHz Supports the station management protocol and frame format (clause 22): -- Basic and extended registers -- Supports next-page function -- Accepts preamble suppression -- Operates up to 12.5 MHz Supports the following management functions via pins if station management is unavailable: -- Speed select -- Encoder/decoder bypass -- Scrambler/descrambler bypass -- Full duplex -- Autonegotiation Supports half- and full-duplex operations Provides four status signals: receive/transmit activity, full duplex, link integrity, and speed indication Powerdown mode for 10 Mbits/s and 100 Mbits/s operation Loopback for 10 Mbits/s and 100 Mbits/s operation 0.35 m low-power CMOS technology 64-pin TQFP Single 5 V power supply
s s
Adjustable squelch level for extended wire line length capability (2 levels) Interfaces with IEEE 802.3u media independent interface (MII) On-chip filtering eliminates the need for external filters Half- and full-duplex operations
s
s
s
s
100 Mbits/s Transceiver
s
Compatible with IEEE 802.3u MII (clause 22), PCS (clause 23), PMA (clause 24), autonegotiation (clause 28), and PMD (clause 25) specifications Scrambler/descrambler bypass Encoder/decoder bypass 3-statable MII in 100 Mbits/s mode Selectable carrier sense signal generation (CRS asserted during either transmission or reception in half duplex, CRS asserted during reception only in full duplex) Selectable MII or 5-bit code group interface Half- or full-duplex operations On-chip filtering and adaptive equalization that eliminates the need for external filters
s s
s s s s
s
s s s s
s s s
* IEEE is a registered trademark of The Institute of Electrical and Electronics Engineers, Inc. Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
Table of Contents
Contents Page
Features .................................................................................................................................................................... 1 10 Mbits/s Transceiver ............................................................................................................................................ 1 100 Mbits/s Transceiver .......................................................................................................................................... 1 General ................................................................................................................................................................... 1 Description.................................................................................................................................................................4 Pin Information and Descriptions............................................................................................................................... 8 MII Station Management .........................................................................................................................................13 Basic Operations...................................................................................................................................................13 MII Management Frames ......................................................................................................................................13 MODE Selection ......................................................................................................................................................23 Absolute Maximum Ratings (TA = 25 C) ................................................................................................................24 Electrical Characteristics .........................................................................................................................................24 Timing Characteristics (Preliminary)........................................................................................................................25 Outline Diagram.......................................................................................................................................................34 64-Pin TQFP .........................................................................................................................................................34 Technical Document Types .....................................................................................................................................35 Ordering Information................................................................................................................................................36
List of Tables
Tables Page
Table 1. MII/Serial Interface Pins (17) ..................................................................................................................... 9 Table 2. MII Management Pins (2) ........................................................................................................................ 10 Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins (4) ................................................................................ 10 Table 4. Ground and Power Pins (21) ................................................................................................................... 11 Table 5. Miscellaneous Pins (20) .......................................................................................................................... 11 Table 5 . Miscellaneous Pins (20) (continued) ....................................................................................................... 12 Table 6. MII Management Frame Fields and Format ............................................................................................. 13 Table 7. MII Management Frame Descriptions ...................................................................................................... 13 Table 8. MII Management Registers (MR) ............................................................................................................. 14 Table 9. MR0--Control Register Bit Descriptions .................................................................................................. 15 Table 10. MR1--Status Register Bit Descriptions ................................................................................................. 16 Table 11. MR2, 3--PHY Identifier Registers (1 and 2) Bit Descriptions ................................................................ 17 Table 12. MR4--Autonegotiation Advertisement Register Bit Descriptions........................................................... 17 Table 13. MR5--Autonegotiation Link Partner (LP) Ability Register Bit Descriptions (Base_Page) ...................... 18 Table 14. MR5--Autonegotiation Link Partner (LP) Ability Register Bit Descriptions (Next_Page) ....................... 18 Table 15. MR6--Autonegotiation Expansion Register Bit Descriptions................................................................. 19 Table 16. MR7--Next_Page Transmit Register Bit Descriptions............................................................................ 19 Table 17. MR28--Device-Specific Register 1 (Status Register) Bit Descriptions ................................................. 20 Table 18. MR29--Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions ........................................... 21 Table 19. MR30--Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions ............................................. 22 Table 20. Operation Modes of LU6612 ................................................................................................................. 23 Table 21. LU6612 Crystal Specifications ............................................................................................................... 23 Table 22 . Absolute Maximum Ratings .................................................................................................................. 24 Table 23 . Operating Conditions ............................................................................................................................ 24 Table 24. dc Characteristics................................................................................................................................... 24 Table 25. MII Management Interface Timing (25 pF Load) .................................................................................... 25 Table 26. MII Data Timing (25 pF Load) ................................................................................................................ 26 Table 27. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK ........................................................................ 28 2 Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Table of Contents (continued)
Tables (continued) Page
Table 28. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK ........................................................... 28 Table 29. Serial 10 Mbits/s Timing for TX_EN, RX/RY, and COL........................................................................... 29 Table 30. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD (25 pF Load) ............... 30 Table 31. Serial 10 Mbits/s Timing for RX_CLK and TX_CLK (25 pF Load).......................................................... 31 Table 32. 100 Mbits/s MII Transmit Timing............................................................................................................. 32 Table 33. 100 Mbits/s MII Receive Timing ............................................................................................................. 33
List of Figures
Figures Page
Figure 1. Functional Block Diagram: Device Overview ............................................................................................ 4 Figure 2. Functional Block Diagram: Device Detail .................................................................................................. 5 Figure 3. Typical Twisted-Pair (TP) Interface ........................................................................................................... 6 Figure 4. Onboard Universal Twisted-Pair Interface Circuit to Interchange Lucent and Quality Semiconductor Inc. Parts .......................................................................................................................... 7 Figure 5. LU6612 Pinout........................................................................................................................................... 8 Figure 6. MDIO Input Timing .................................................................................................................................. 25 Figure 7. MDIO Output Timing ............................................................................................................................... 25 Figure 8. MDIO During TA (Turnaround) of a Read Transaction ........................................................................... 25 Figure 9. MII Timing Requirements for LU6612 ..................................................................................................... 27 Figure 10. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK ...................................................................... 28 Figure 11. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK.......................................................... 28 Figure 12. Serial 10 Mbits/s Timing for TX_EN, RX/RY, and COL ......................................................................... 29 Figure 13. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD ................................... 30 Figure 14. Serial 10 Mbits/s Timing Diagram for RX_CLK and TX_CLK................................................................ 31 Figure 15. 100 Mbits/s MII Transmit Timing ........................................................................................................... 32 Figure 16. 100 Mbits/s MII Receive Timing ............................................................................................................ 33
Lucent Technologies Inc.
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LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
Autonegotiation of IEEE 802.3u. MII management of IEEE 802.3u. Physical medium dependent (PMD) of IEEE 802.3u.
Description
The LU6612 is a single-channel, single-chip complete transceiver designed specifically for dual-speed 10Base-T and 100Base-TX repeaters and switches. LU6612 implements:
s s s
s s s
The 10Base-T transceiver function of IEEE 802.3u. The physical coding sublayer (PCS) of IEEE 802.3u. The physical medium attachment (PMA) of IEEE 802.3u.
This device supports operation over category 3 unshielded twisted-pair (UTP) cable, according to IEEE 802.3u 10Base-T specification, and over category 5, Type 1, UTP and Type 1 shielded twisted-pair cable, according to IEEE 802.3u 100Base-X specification. Figure 1 illustrates a functional overview of the LU6612 while Figure 2 details the functions. Figure 3 shows how the LU6612 interfaces to the twisted pair.
MII/SERIAL INTERFACE
MANAGEMENT PMA PCS
TX PMD DRIVER AND AUTONEGOTIATION FILTERS
25 MHz LSCLK 25 MHz DPLL 125 MHz 20 MHz 10 Mbits/s TRANSCEIVER DRIVER AND FILTERS
5-5600(F).r1
TO/FROM MAGNETICS MUX
Figure 1. Functional Block Diagram: Device Overview
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Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Description (continued)
100 Mbits/s TRANSCEIVER TXD[3:0] 4B/5B ENCODER FAR-END FAULT GEN PMD TX
SCRAMBLER
PDT
CRS COL RXD[3:0] RX_DV RX_ER/RXD[4] RX_CLK TX_CLK TXD[3:0] TX_EN TX_ER/TXD[4]
TX STATE MACHINE
SD COLLISION SD DETECT
RX STATE MACHINE
SD
TX/TY DCRU
MII INTERFACE
MII
CAR_STAT CIM RXERR_ST CARRIER DETECT ALIGNER DESCRAMBLER PDR SD PMD RX
5B/4B DECODER FAR-END FAULT DETECT
REF10 RXC RXD TXC TEN TXD CLK20 MDC MDIO
SERIAL INTERFACE
RX/RY 10 Mbits/s TRANSCEIVER LC100 LC10 LS10 LS100
MANAGEMENT INTERFACE
MII MANAGEMENT 25 MHz
AUTONEGOTIATION AND LINK MONITOR
LSCLK
DPLL
125 MHz 20 MHZ
5-5136(F).cr1
Figure 2. Functional Block Diagram: Device Detail
Lucent Technologies Inc.
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LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
Description (continued)
VDD RJ-45 8 TX 50 220 1:1 1 2 75 0.01 F RX 50 50 64 RY 1:1 0.01 F 0.01 F 75 0.001 F 75 75 6 7 8 0.001 F 5 63 3 4
50 9 LU6612 TY
220
0.01 F
5-5433.i.r3
Figure 3. Typical Twisted-Pair (TP) Interface
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Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Description (continued)
VDD
Q=0 L = OPEN 8 TX L = 50 Q = 86.6 L=0 Q = OPEN
VDD RJ-45 L = 1:1; Q = 1.25:1 1 L = 220 Q = 39
2
L = 50 Q = 86.6 9 LU6612 QS6612 63 RX Q = 60 L = 50 L = 50 Q=0 64 RY L=0 Q = 20 TY
L = 220 Q = OPEN L = 0.01 Q = 0.1 F
L = Q = 75
3
4
5 L = Q = 1:1 6
7 L=0 Q = 20
8 L = Q = 75
L = 0.01 F L = 0.01 F Q = OPEN Q = 0.1 F
L = Q = 75
Q=0 L = OPEN Q=0 L = OPEN
L = Q = 75
L=0 Q = OPEN
L=0 Q = OPEN
L = 0.01 F Q = 1000 pF
L = 0.001 F
L = 0.001 F
5-5433.j
Key: L = Lucent's LU6612. Q = Quality Semiconductor Inc. QS6612.
Figure 4. Onboard Universal Twisted-Pair Interface Circuit to Interchange Lucent and Quality Semiconductor Inc. Parts
Lucent Technologies Inc.
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LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
Pin Information
FUDUPLED/PHYAD[3] SPEEDLED/PHYAD[2]
GNDEQAP
BGREF[0]
BGREF[1]
VCCEQAP
GNDREC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
VCCBG ISET_100 GNDBG LINKLED/PHYAD[0] ACTLED/PHYAD[1] VCCIOA GNDIOA TX TY GNDT VCCT CLKREF GNDBT VCCBT TEST[0] TEST[1]
49
VCCDIGB
MODE[2]
MODE[1]
MODE[0]
GNDIOB
VCCREC
VCCIOB
RX
RY
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43
GNDDIGB TX_CLK RX_ER/RXD[4] RX_DV RX_CLK COL CRS GNDIOC RXD[0] RXD[1] RXD[2] RXD[3] GNDDIGA VCCDIGA TXD[0] TXD[1]
LU6612
42 41 40 39 38 37 36 35 34 33
ISET_10
LSCLK1
LSCLK2
VCCPLL
RX_EN
PCSEN
GNDPLL
TX_ER/TXD[4]
TEST[2]
RESET
TX_EN
MDC
TXD[3]
PHYAD[4]
TXD[2]
MDIO
5-5866.r2
Figure 5. LU6612 Pinout
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Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Pin Information (continued)
Pin Descriptions
Table 1. MII/Serial Interface Pins (17) Signal COL Type O Pin 43 Description
CRS
O
RX_CLK
O
RXD[3:0]
O
RX_DV
O
RX_ER/ RXD[4]
O
TX_CLK
O
TXD[3:0] TX_EN
I I
Collision Detect. This signal signifies in half-duplex mode that a collision has occurred on the network. COL is asserted high whenever there is transmit and receive activity on the UTP media. COL is the logical AND of TX_EN and receive activity, and is an asynchronous output. When SERIAL_SEL (register 30, bit 1) is high and in 10Base-T mode, this signal indicates the jabber timer has expired. This signal is held low in full-duplex mode. 42 Carrier Sense. When CRS_SEL (register 29, bit 10) is low, CRS is asserted high when either the transmit or receive is nonidle. This signal remains asserted throughout a collision condition. When CRS_SEL (register 29, bit 10) is high, CRS is asserted on receive activity only. 44 Receive Clock. 25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output in 10 Mbits/s nibble mode, 10 MHz in 10 Mbits/s serial mode. RX_CLK has a worst-case 45/55 duty cycle. RX_CLK provides the timing reference for the transfer of RX_DV, RXD, and RX_ER signals. 37:40 Receive Data. 4-bit parallel data outputs that are synchronous to the falling edge of RX_CLK. When RX_ER is asserted high in 100 Mbits/s mode, an error code will be presented on RXD[3:0] where appropriate. The codes are as follows: s Packet errors: ERROR_CODES = 2h; s Link errors: ERROR_CODES = 3h (Packet and link error codes will only be repeated if registers [29.9] and [29.8] are enabled.); s Premature end errors: ERROR_CODES = 4h; s Code errors: ERROR_CODES = 5h. When SERIAL_SEL (register 30, bit 1) is active-high and 10 Mbits/s mode is selected, RXD[0] is used for data output and RXD[3:1] are 3-stated. 45 Receive Data Valid. When this pin is high, it indicates the LU6612 is recovering and decoding valid nibbles on RXD[3:0], and the data is synchronous with RX_CLK. RX_DV is synchronous with RX_CLK. This pin is not used in serial 10 Mbits/s mode. 46 Receive Error. When high, RX_ER indicates the LU6612 has detected a coding error in the frame presently being transferred. RX_ER is synchronous with RX_CLK. When the encode/decode bypass (EDB) is selected through the MII management interface, this output serves as the RXD[4] output. This pin is only valid when LU6612 is in 100 Mbits/s mode. 47 Transmit Clock. 25 MHz clock output in 100 Mbits/s mode, 2.5 MHz output in 10 Mbits/s MII mode, 10 MHz output in 10 Mbits/s serial mode. TX_CLK provides timing reference for the transfer of the TX_EN, TXD, and TX_ER signals. These signals are sampled on the rising edge of TX_CLK. 31:34 Transmit Data. 4-bit parallel input synchronous with TX_CLK. When SERIAL_SEL (register 30, bit 1) is active-high and 10 Mbits/s mode is selected, only TXD[0] is valid. 30 Transmit Enable. When driven high, this signal indicates there is valid data on TXD[3:0]. TX_EN is synchronous with TX_CLK. When SERIAL_SEL (register 30, bit 1) is active-high and 10 Mbits/s mode is selected, this pin indicates there is valid data on TXD[0].
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LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
Pin Information (continued)
Table 1. MII/Serial Interface Pins (17) (continued) Signal TX_ER/ TXD[4] Type I Pin 29 Description Transmit Coding Error. When driven high, this signal causes the encoder to intentionally corrupt the byte being transmitted across the MII (00100 will be transmitted). When the encoder/decoder bypass bit is set, this input serves as the TXD[4] input. When in 10 Mbits/s mode and SERIAL_SEL (register 30, bit 1) is active-high, this pin is ignored. Receive Enable. When this pin is high, the outputs (RXD[3:0], RX_ER, RX_CLK, RX_DV) are enabled. This pin has an internal 100 k pull-up resistor.
RX_EN
I
28
Table 2. MII Management Pins (2) Signal MDC Type I Pin 26 Description Management Data Clock. This is the timing reference for the transfer of data on the MDIO signal. This signal may be asynchronous to RX_CLK and TX_CLK. The standard clock rate is 2.5 MHz, the maximum clock rate is 12.5 MHz. When running MDC above 6.25 MHz, MDC must be synchronous with LSCLK and have a setup time of 15 ns and a hold time of 5 ns with respect to LSCLK. Management Data Input/Output. This I/O is used to transfer control and status information between LU6612 and the station management. Control information is driven by the station management synchronous with MDC. Status information is driven by the LU6612 synchronous with MDC.
MDIO
IO
25
Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Pins (4) Signal RX RY TX TY Type I I O O Pin 63 62 8 9 Description Received Data. Positive differential received 125 Mbaud MLT3 or 10 Mbaud Manchester data from magnetics. Received Data. Negative differential received 125 Mbaud MLT3 or 10 Mbaud Manchester data from magnetics. Transmit Data. Positive differential transmit 125 Mbaud MLT3 or 10 Mbaud Manchester data to magnetics. Transmit Data. Negative differential transmit 125 Mbaud MLT3 or 10 Mbaud Manchester data to magnetics.
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Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Pin Information (continued)
Table 4. Ground and Power Pins (21) Signal VCCIOA GNDIOA VCCIOB GNDIOB GNDIOC VCCDIGA GNDDIGA VCCDIGB GNDDIGB VCCREC GNDREC VCCPLL GNDPLL VCCT GNDT VCCEQAP GNDEQAP VCCBG GNDBG VCCBT GNDBT Type PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR PWR Pin 6 7 54 53 41 35 36 49 48 60 59 20 23 11 10 61 64 1 3 14 13 Description Digital +5 V power supply for I/O Digital ground for I/O Digital +5 V power supply for I/O Digital ground for I/O Digital ground for I/O Digital +5 V power supply for logic Digital ground for logic Digital +5 V power supply for logic Digital ground for logic Digital +5 V power supply for clock recovery circuit Digital ground for clock recovery circuit Analog +5 V power supply for 10 MHz and 100 MHz PLL clock synthesizer Analog ground for 10 MHz and 100 MHz PLL clock synthesizer Analog +5 V power supply for transmitter Analog ground for transmitter Analog +5 V power supply for equalizer and adaptation circuit Analog ground for adaptation circuit. Analog +5 V power supply for band-gap circuit Analog ground band-gap circuit Analog +5 V power supply for 10Base-T transmitter Analog ground for 10Base-T transmitter
Table 5. Miscellaneous Pins (20)
Signal LSCLK1 LSCLK2 Type* I O Pin 21 22 Description Local Symbol Clock. 25 MHz clock, 100 ppm, 40%--60% duty cycle. This input is connected to one terminal of a 25 MHz crystal or an external 25 MHz clock source. Local Symbol Clock. 25 MHz crystal feedback. This output is connected to the other terminal of a 25 MHz crystal or an external 25 MHz. If LSCLK1 is driven from an external clock source, LSCLK2 is left unconnected. Link LED. This pin indicates good link status. At powerup/reset, this pin is sampled as input and to set the PHYAD[0] bit. If pulled high through a resistor, this pin will set PHYAD[0] to a high or if pulled low through a resistor, will set PHYAD[0] to a zero. When this pin is pulled high the LED output will be active-low, when pulled low the LED output will be active-high. Activity LED. This pin indicates transmit/receive activity. At powerup/reset, this pin is sampled as input to set the PHYAD[1] bit. If pulled high through a resistor, this pin will set PHYAD[1] to a high or if pulled low through a resistor, will set PHYAD[1] to a zero. When this pin is pulled high the LED output will be active-low, when pulled low the LED output will be active-high.
LINKLED/ PHYAD[0]
I/O
4
ACTLED/ PHYAD[1]
I/O
5
* indicates there is an internal pull-up; indicates there is an internal pull-down.
Lucent Technologies Inc.
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LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
Pin Information (continued)
Table 5. Miscellaneous Pins (20) (continued)
Signal SPEEDLED/ PHYAD[2] Type* I/O Pin 56 Description
FUDUPLED/ PHYAD[3]
I/O
PHYAD[4]
I
MODE[2:0]
I
TEST[0] TEST[2:1] CLKREF RESET
I I I I
Speed LED. This pin indicates the operating speed of LU6612: s LED is active when in 100 Mbits/s operation. s LED is not active when in 10 Mbits/s operation. At powerup/reset, this pin is sampled as input and to set the PHYAD[2] bit. If pulled high through a resistor, this pin will set PHYAD[2] to a high or if pulled low through a resistor, will set PHYAD[2] to a zero. When this pin is pulled high, the LED output will be active-low, when pulled low, the LED output will be active-high. 55 Full-Duplex LED. This pin indicates the operating mode of LU6612 and is only valid when link is up: s LED is active when in full-duplex mode of operation. s LED is not active when in half-duplex mode of operation. At powerup/reset, this pin is sampled as an input to set the PHYAD[3] bit. If pulled high through a resistor, this pin will set PHYAD[3] to a high or if pulled low through a resistor, will set PHYAD[3] to a zero. When this pin is pulled high, the LED output will be active-low, when pulled low, the LED output will be active-high. 17 PHYAD[4]. At powerup/reset, this pin is sampled as an input to set the PHYAD[4] bit. If pulled high through a resistor, this pin will set PHYAD[4] to a high or if pulled low through a resistor, will set PHYAD[4] to a zero. This pin has an internal 100 k pullup resistor. 52:50 Mode Selection. These pins carry encoded signals that are latched into the LU6612 upon powerup/reset and define specific modes of operation: half/full duplex, autonegotiation enabled/disabled, and transceiver isolation. Refer to Table 20 for the various modes and how various registers are affected. Pins [52:50] have internal 100 k pullups. If left floating, LU6612 will default to all capable, autonegotiation enabled mode. 15 Test Enable Pin for Factory Testing. This pin has an internal 100 k pull-down resistor. The pin can be either left floating or tied down. 19, Test Enable Pin for Factory Testing. These two pins have internal 50 k pull-down 16 resistors. These pins can either be left floating or tied low. 12 Clock Reference. Connect this pin to a 1 nF 10% capacitor to ground. Full Chip Reset (Active-Low). Reset is an active-low signal. Reset must be asserted low for at least five LSCLK cycles. The LU6612 will come out of reset after 400 s. LSCLK1 must remain running during reset. 57:58 Band-Gap Reference. Connect these pins to a 24.9 k 1% resistor to ground. The parasitic load capacitance should be less than 15 pF. Current Set 100 Mbits/s. An external reference resistor (24.9 k) is placed from this 2 pin to ground to set the 100 Mbits/s TP driver transmit output level. 24 Current Set 10 Mbits/s. An external reference resistor (22.1 k) is placed from this pin to ground to set the 10 Mbits/s TP driver transmit output level. 27 18 PCS Enable (Active-Low). When this pin is active-low, the encoded 5-bit symbols appear on RXD[4:0] and TXD[4:0]. When this pin high, 4-bit data appears on RXD[3:0] and TXD[3:0]. When PCSEN is low, LU6612 bypasses the 4B5B encoder/ decoder, the align function, the scrambler/descrambler, and does not detect and generate J/K and R/T code groups at the start or end of frame. This pin has an internal 100 k pull-up.
BGREF[1:0] ISET_100 ISET_10 PCSEN
I I I I
* indicates there is an internal pull-up; indicates there is an internal pull-down.
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Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
MII Station Management
Basic Operations
The primary function of station management is to transfer control and status information about the LU6612 to a management entity. This function is accomplished by the MDC clock input, which has a maximum frequency of 12.5 MHz, along with the MDIO pin. The management interface (MII) uses MDC and MDIO to physically transport information between the PHY and the station management entity. A specific set of registers and their contents (described in Table 8) defines the nature of the information transferred across this interface. Frames transmitted on the MII management interface will have the frame structure shown in Table 6. The order of bit transmission is from left to right. Note that reading and writing of the management register must be completed without interruption.
MII Management Frames
The fields and format for management frames are described in the following tables. Table 6. MII Management Frame Fields and Format Read/Write (R/W) R W Pre 1...1 1...1 ST 01 01 OP 10 01 PHYADD AAAAA AAAAA REGAD RRRRR RRRRR TA Z0 10 DATA DDDDDDDDDDDDDDDD DDDDDDDDDDDDDDDD Idle Z Z
Table 7. MII Management Frame Descriptions Field Pre ST OP PHYADD Description Preamble. The preamble is a series of 32 1s. The LU6612 will accept frames with no preamble. This is indicated by a 1 in register 1, bit 6. Start of Frame. The start of frame is indicated by a 01 pattern. Operation Code. The operation code for a read transaction is 10. The operation code for a write transaction is 01. PHY Address. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address bit transmitted and received is the MSB of the address. A station management entity, which is attached to multiple PHY entities, must have prior knowledge of the appropriate PHY address for each entity. The address 00000 is the broadcast address. This address will produce a match regardless of the local address. Register Address. The register address is 5 bits, allowing for 32 unique registers within each PHY. The first register address bit transmitted and received is the MSB of the address. Turnaround. The turnaround time is a 2-bit time spacing between the register address field and the data field of a frame to avoid drive contention on MDIO during a read transaction. During a write to the LU6612, these bits are driven to a 10 by the station. During a read, the MDIO is not driven during the first bit time and is driven to a 0 by the LU6612 during the second bit time. Data. The data field is 16 bits. The first bit transmitted and received is bit 15 of the register being addressed.
REGAD TA
DATA
Lucent Technologies Inc.
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LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
MII Station Management (continued)
Register Overview The MII management 16-bit register (MR) set is implemented as described in Table 8 below. Table 8. MII Management Registers (MR) Register Address 0 1 2 3 4 5 5 6 7 8--27 28 29 30 Symbol MR0 MR1 MR2 MR3 MR4 MR5 MR5 MR6 MR7 MR8--MR27 MR28 MR29 MR30 Name Control Register Status Register PHY Identifier Register 1 PHY Identifier Register 2 Autonegotiation Advertisement Register Autonegotiation Link Partner Ability Register (Base_Page) Autonegotiation Link Partner Ability Register (Next_Page) Autonegotiation Expansion Register Next-Page Transmit Register Reserved Device Specific Register 1 Device Specific Register 2 Device Specific Register 3 Default (Hex Code) 3000 7849 0180 7641 01E1 0000 -- 0000 0000 0000 0000 1000 0000
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Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
MII Station Management (continued)
This section provides a detailed discussion of each management register and its bit definitions. Table 9. MR0--Control Register Bit Descriptions Bit1 0.15 (SW_RESET) 0.14 (LOOPBACK) Type2 R/W R/W Description Reset. Setting this bit to a 1 will reset the LU6612. All registers will be set to their default state. This bit is self-clearing. The default is 0. Loopback. When this bit is set to 1, no data transmission will take place on the media. Any receive data will be ignored. The loopback signal path will contain all circuitry up to, but not including, the PMD. The autonegotiation must be turned off, before loopback can be initiated, transmit data can be started 2 ms after loopback is initiated. The default value is a 0. Speed Selection. The value of this bit reflects the current speed of operation (1 = 100 Mbits/s; 0 = 10 Mbits/s). This bit will only affect operating speed when the autonegotiation enable bit (register 0, bit 12) is disabled (0). This bit is ignored when autonegotiation is enabled (register 0, bit 12). The bit is set high when MODE[2:0] is 010 or 011 or 100. The default is 1. Autonegotiation Enable. The autonegotiation process will be enabled by setting this bit to a 1. This bit overrides SPEED100 bit (register 0, bit 13) and FULL_DUP bit (register 0, bit 8). This bit is set high when MODE[2:0] is 100 or 111. Autonegotiation must be disabled before loopback can be initiated. The default state is a 1. Powerdown. The LU6612 may be placed in a low-power state by setting this bit to a 1, both the 10 Mbits/s transceiver and the 100 Mbits/s transceiver will be powered down. While in the powerdown state, the LU6612 will respond to management transactions. The default state is a 0. Isolate. When this bit is set to a 1, the MII outputs will be brought to the highimpedance state. The default state is a 0. Restart Autonegotiation. Normally, the autonegotiation process is started at powerup. The process may be restarted by setting this bit to a 1. The default state is a 0. The NWAYDONE bit (register 1, bit 5) is reset when this bit goes to a 1. This bit is self-cleared when autonegotiation restarts. Duplex Mode. This bit reflects the mode of operation (1 = full duplex; 0 = half duplex). This bit is ignored when the autonegotiation enable bit (register 0, bit 12) is enabled. The default state is a 0. This bit is set as a 1 during powerup/ reset, when MODE[2:0] is 001 or 011. Collision Test. When this bit is set to a 1, the LU6612 will assert the COL signal in response to TX_EN. This bit should only be set when in loopback mode. Reserved. All bits will read 0.
0.13 (SPEED100)
R/W
0.12 (NWAY_ENA)
R/W
0.11 (PWRDN)
R/W
0.10 (ISOLATE) 0.9 (REDONWAY)
R/W R/W
0.8 (FULL_DUP)
R/W
0.7 (COLTST) 0.6:0
R/W NA
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters. 2. R = read, W = write, NA = not applicable.
Lucent Technologies Inc.
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LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
MII Station Management (continued)
Table 10. MR1--Status Register Bit Descriptions Bit1 1.15 (T4ABLE) Type2 R Description 100Base-T4 Ability. This bit will always be a 0. 0: Not able 1: Able 100Base-TX Full-Duplex Ability. This bit will always be a 1. 0: Not able 1: Able 100Base-TX Half-Duplex Ability. This bit will always be a 1. 0: Not able 1: Able 10Base-T Full-Duplex Ability. This bit will always be a 1. 0: Not able 1: Able 10Base-T Half-Duplex Ability. This bit will always be a 1. 0: Not able 1: Able Reserved. All bits will read as a 0. Suppress Preamble. This bit is set to a 1, indicating that the LU6612 accepts management frames with the preamble suppressed. (This function is not supported by QS6611.) Autonegotiation Complete. When this bit is a 1, it indicates the autonegotiation process has been completed. The contents of registers MR4, MR5, MR6, and MR7 are now valid. The default value is a 0. This bit is reset when autonegotiation is started. Remote Fault. When this bit is a 1, it indicates a remote fault has been detected. This bit will remain set until cleared by reading the register. The default is a 0. Autonegotiation Ability. When this bit is a 1, it indicates the ability to perform autonegotiation. The value of this bit is always a 1. Link Status. When this bit is a 1, it indicates a valid link has been established. This bit has a latching function: a link failure will cause the bit to clear and stay cleared until it has been read via the management interface. Jabber Detect. This bit will be a 1 whenever a jabber condition is detected. It will remain set until it is read, and the jabber condition no longer exists. Extended Capability. This bit indicates that the LU6612 supports the extended register set (MR2 and beyond). It will always read a 1.
1.14 (TXFULDUP)
R
1.13 (TXHAFDUP)
R
1.12 (ENFULDUP)
R
1.11 (ENHAFDUP)
R
1.10:7 1.6 (NO_PA_OK)
R R
1.5 (NWAYDONE)
R
1.4 (REM_FLT) 1.3 (NWAYABLE) 1.2 (LSTAT_OK)
R R R
1.1 (JABBER) 1.0 (EXT_ABLE)
R R
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters. 2. R = read.
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Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
MII Station Management (continued)
Table 11. MR2, 3--PHY Identifier Registers (1 and 2) Bit Descriptions Bit1 2.15:0 (OUI[3:18]) Type2 R Description Organizationally Unique Identifier. The third through the 24th bits of the OUI assigned to the PHY manufacturer by the IEEE are to be placed in bits 2.15:0 and 3.15:10. The value for bits 15:0 of register 2 is 0180h. Organizationally Unique Identifier. The remaining 6 bits of the OUI. The value for bits 15:10 of register 3 is 1Dh. Model Number. 6-bit model number of the device. The model number is 12 decimal. Revision Number. The value of the present revision number. The value is 0001b for the first version.
3.15:10 (OUI[19:24]) 3.9:4 (MODEL[5:0]) 3.3:0 (VERSION[3:0])
R R R
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters. 2. R = read.
Table 12. MR4--Autonegotiation Advertisement Register Bit Descriptions Bit1 4.15 (NEXT_PAGE) Type2 R/W Description Next Page. The next page function is activated by setting this bit to a 1. This will allow the exchange of arbitrary pieces of data. Data is carried by optional next pages of information. (This function is not supported by QS6611.) Acknowledge. This bit is written to a logic zero and ignored on read. Remote Fault. When set to 1, the LU6612 indicates to the link partner a remote fault condition. Pause. When set to 1, indicates that the LU6612 wishes to exchange flow control information with its link partner. 100Base-T4. This bit should always be set to a 0. 100Base-TX Full Duplex. If written to 1, autonegotiation will advertise that the LU6612 is capable of 100Base-TX full-duplex operation. This bit is set high when MODE[2:0] is 111. 100Base-TX. If written to 1, autonegotiation will advertise that the LU6612 is capable of 100Base-TX operation. 10Base-T Full Duplex. If written to 1, autonegotiation will advertise that the LU6612 is capable of 10Base-T full-duplex operation. This bit is set high when MODE[2:0] is 111. 10Base-T. If written to 1, autonegotiation will advertise that the LU6612 is capable of 10Base-T operation. This bit is set high when MODE[2:0] is 111. Selector Field. Reset with the value 00001 for IEEE 802.3.
4.14 (ACK) 4.13 (REM_FAULT) 4.12:10 (PAUSE) 4.9 (100BASET4) 4.8 (100BASET_FD)
R/W R/W R/W R/W R/W
4.7 (100BASETX) 4.6 (10BASET_FD)
R/W R/W
4.5 (10BASET) 4.4:0 (SELECT)
R/W R/W
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters. 2. R = read, W = write.
Lucent Technologies Inc.
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LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
MII Station Management (continued)
Table 13. MR5--Autonegotiation Link Partner (LP) Ability Register Bit Descriptions (Base_Page) Bit1 5.15 (LP_NEXT_PAGE) 5.14 (LP_ACK) Type2 R R Description Link Partner Next Page. When this bit is set to 1, it indicates that the link partner wishes to engage in next page exchange. Link Partner Acknowledge. When this bit is set to 1, it indicates that the link partner has successfully received at least three consecutive and consistent FLP bursts. Link Partner Remote Fault. When this bit is set to 1, it indicates that the link partner has a fault. Reserved. These bits are reserved. Link Partner 100Base-T4. When this bit is set to 1, it indicates that link partner is capable of 100Base-T4 operation. Link Partner 100Base-TX Full Duplex. When this bit is set to 1, it indicates that link partner is capable of 100Base-TX full-duplex operation. Link Partner 100Base-TX. When this bit is set to 1, it indicates that link partner is capable of 100Base-TX operation. Link Partner 10Base-T Full Duplex. When this bit is set to 1, it indicates that link partner is capable of 10Base-T full-duplex operation. Link Partner 10Base-T. When this bit is set to 1, it indicates that link partner is capable of 10Base-T operation. Selector Field. This field contains the type of message sent by the link partner. For IEEE 802.3 compliant link partners, this field should read 00001.
5.13 (LP_REM_FAULT) 5.12:10 5.9 (LP_100BASET4) 5.8 (LP_100BASET_FD) 5.7 (LP_100BASETX) 5.6 (LP_10BASET_FD) 5.5 (LP_10BASET) 5.4:0 (LP_SELECT)
R R R R R R R R
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters. 2. R = read.
Table 14. MR5--Autonegotiation Link Partner (LP) Ability Register Bit Descriptions (Next_Page) Bit1 5.15 (LP_NEXT_PAGE) 5.14 (LP_ACK) 5.13 (LP_MES_PAGE) 5.12 (LP_ACK2) Type2 R R R R Description Next Page. When this bit is set to a logic 0, it indicates that this is the last page to be transmitted. A logic 1 indicates that additional pages will follow. Acknowledge. When this bit is set to a logic 1, it indicates that the link partner has successfully received its partner's link code word. Message Page. This bit is used by the Next_Page function to differentiate a Message Page (logic one) from an unformatted page (logic zero). Acknowledge 2. This bit is used by Next_Page function to indicate that a device has the ability to comply with the message (logic one) or not (logic zero). Toggle. This bit is used by the arbitration function to ensure synchronization with the link partner during next page exchange. Logic 0 indicates that the previous value of the transmitted link code word was logic 1. Logic 1 indicates that the previous value of the transmitted link code word was logic 0. Message/Unformatted Code Field. With these 11 bits, there are 2048 possible messages. Message code field definitions are described in annex 28C of the IEEE 802.3u standard.
5.11 (LP_TOGGLE)
R
5.10:0 (MCF)
R
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters. 2. R = read.
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Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
MII Station Management (continued)
Table 15. MR6--Autonegotiation Expansion Register Bit Descriptions Bit1 6.15:5 6.4 (PAR_DET_FAULT) Type2 R R/LH Description
6.3 (LP_NEXT_PAGE_ABLE) 6.2 (NEXT_PAGE_ABLE) 6.1 (PAGE_REC) 6.0 (LP_NWAY_ABLE)
Reserved. Parallel Detection Fault. When this bit is set to 1, it indicates that a fault has been detected in the parallel detection function. This fault is due to more than one technology detecting concurrent link conditions. This bit can only be cleared by reading this register. Link Partner Next Page Able. When this bit is set to 1, it indicates that the R link partner supports the next page function. Next Page Able. This bit is set to 1, indicating that this device supports the R next page function. R/LH Page Received. When this bit is set to 1, it indicates that a next page has been received. Link Partner Autonegotiation Capable. When this bit is set to 1, it indiR cates that the link partner is autonegotiation capable.
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters. 2. R = read, LH = latched high.
Table 16. MR7--Next_Page Transmit Register Bit Descriptions Bit1 7.15 (NEXT_PAGE) Type2 R/W Description Next Page. This bit indicates whether or not this is the last next page to be transmitted. When this bit is 0, it indicates that this is the last page. When this bit is 1, it indicates there is an additional next page. Acknowledge. This bit is the acknowledge bit from the link code word. Message Page. This bit is used to differentiate a message page from an unformatted page. When this bit is 0, it indicates an unformatted page. When this bit is 1, it indicates a formatted page. Acknowledge 2. This bit is used by the next page function to indicate that a device has the ability to comply with the message. Acknowledge 2 will be set as follows: s When this bit is 0, it indicates the device cannot comply with the message. s When this bit is 1, it indicates the device will comply with the message. Toggle. This bit is used by the arbitration function to ensure synchronization with the link partner during next page exchange. This bit will always take the opposite value of the toggle bit in the previously exchanged link code word: s If the bit is a logic 0, the previous value of the transmitted link code word was a logic 1. s If the bit is a 1, the previous value of the transmitted link code word was a 0. The initial value of the toggle bit in the first next page transmitted is the inverse of the value of bit 11 in the base link code word and, therefore, may assume a value of 1 or 0. Message/Unformatted Code Field. With these 11 bits, there are 2048 possible messages. Message code field definitions are described in annex 28C of the IEEE 802.3u standard.
7.14 (ACK) 7.13 (MESSAGE)
R R/W
7.12 (ACK2)
R/W
7.11 (TOGGLE)
R
7.10:0 (MCF)
R/W
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters. 2. R = read, W = write.
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LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
MII Station Management (continued)
Table 17. MR28--Device-Specific Register 1 (Status Register) Bit Descriptions Bit1 28.15:9 (R28[15:9]) 28.8 (BAD_FRM) Type2 R R/LH Description Unused. Read as 0. Bad Frame. If this bit is a 1, it indicates a packet has been received without an SFD. This bit is only valid in 10 Mbits/s mode. This bit is latching high and will only clear after it has been read or the device has been reset. The default is 0. Code Violation. When this bit is a 1, it indicates a Manchester code violation has occurred. The error code will be output on the RXD lines. Refer to Table 1 for a detailed description of the RXD pin error codes. This bit is only valid in 10 Mbits/s mode. This bit is latching high and will only clear after it has been read or the device has been reset. The default is 0. Autopolarity Status. When register 30, bit 3 is set and this bit is a 1, it indicates the LU6612 has detected and corrected a polarity reversal on the twisted pair. If the APF_EN bit (register 30, bit 3) is set, the reversal will be corrected inside the LU6612. This bit is not valid in 100 Mbits/s operation. The default is 0. Disconnect. If this bit is a 1, it indicates a disconnect. This bit will latch high until read. This bit is only valid in 100 Mbits/s mode. The default is 0. Unlocked. Indicates that the TX scrambler lost lock. This bit will latch high until read. This bit is only valid in 100 Mbits/s mode. The default is 0. RX Error Status. Indicates a false carrier. This bit will latch high until read. This bit is only valid in 100 Mbits/s mode. The default is 0. Force Jam. This bit will latch high until read. This bit is only valid in 100 Mbits/s mode. The default is 0. Link Up 100. This bit, when set to a 1, indicates a 100 Mbits/s transceiver is up and operational. The default is 0. Link Up 10. This bit, when set to a 1, indicates a 10 Mbits/s transceiver is up and operational. The default is 0.
28.7 (CODE)
R/LH
28.6 (APS)
R
28.5 (DISCON) 28.4 (UNLOCKED) 28.3 (RXERR_ST) 28.2 (FRC_JAM) 28.1 (LNK100UP) 28.0 (LNK10UP)
R/LH R/LH R/LH R/LH R R
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters. 2. R = read, LH = latched high.
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Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
MII Station Management (continued)
Table 18. MR29--Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions Bit1 29.15 (LOCALRST) Type2 R/W Description Management Reset. This is the local management reset bit. Writing a logic 1 to this bit will cause the lower 16 registers and registers 28 and 29 to be reset to their default values. This bit is self-clearing. The default is 0. Generic Reset 1. This register is used for manufacture test only. The default is 0. Generic Reset 2. This register is used for manufacture test only. The default is 0. 100 Mbits/s Transmitter Off. When this bit is set to 0, it forces RX low and RY high. This bit defaults to 1. Reserved. Program to zero. Carrier Sense Select. CRS will be asserted on receive only when this bit is set to a 1. If this bit is set to logic 0, CRS will be asserted on receive or transmit. The default is 0. Link Error Indication. When this bit is a 1, a link error code will be reported on RXD[3:0] of the LU6612 when RX_ER is asserted on the MII. The specific error codes are listed in the RXD pin description. If it is 0, it will disable this function. The default is 0. Packet Error Indication Enable. When this bit is a 1, a packet error code, which indicates that the scrambler is not locked, will be reported on RXD[3:0] of the LU6612 when RX_ER is asserted on the MII. When this bit is 0, it will disable this function. The default is 0. Reserved. This bit must remain as a zero. The default is 0. Encoder/Decoder Bypass. When this bit is set to 1, the 4B/5B encoder and 5B/4B decoder function will be disabled. The default is a zero. At powerup/reset, if PCSEN is strapped low, then this bit is set to a 1. The default is 0. Symbol Aligner Bypass. When this bit is set to 1, the aligner function will be disabled. The default is 0. Scrambler/Descrambler Bypass. When this bit is set to 1, the scrambling/ descrambling functions will be disabled. The default is a zero. At powerup/reset, if PCSEN is strapped low, then this bit is set to a 1. The default is 0. Carrier Integrity Enable. When this bit is set to a 1, carrier integrity is enabled. (This function is not supported by QS6611.) The default is 0. Jam Enable. When this bit is a 1, it enables JAM associated with carrier integrity to be ORed with COL. The default is 0. Reserved. This bit must remain as a zero. The default is 0. Reserved. This bit must remain as a zero. The default is 0.
29.14 (RST1) 29.13 (RST2) 29.12 (100OFF) 29.11 29.10 (CRS_SEL)
R/W R/W R/W R/W R/W
29.9 (LINK_ERR)
R/W
29.8 (PKT_ERR)
R/W
29.7 (RESERVED) 29.6 (EDB)
R/W R/W
29.5 (SAB) 29.4 (SDB)
R/W R/W
29.3 (CARIN_EN) 29.2 (JAM_COL) 29.1 (RESERVED) 29.0 (RESERVED)
R/W R/W R/W R/W
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters. 2. R = read, W = write.
Lucent Technologies Inc.
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LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
MII Station Management (continued)
Table 19. MR30--Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions Bit1 30.15:6 (R30[15:6]) 30.5 (HBT_EN) 30.4 (ELL_EN) Type2 R/W R/W R/W Description Unused. Read as 0. Heartbeat Enable. When this bit is a 1, the heartbeat function will be enabled. Valid in 10 Mbits/s mode only. The default is 0. Extended Line Length Enable. When this bit is a 1, the receive squelch levels are reduced from a nominal 435 mV to 350 mV, allowing reception of signals with a lower amplitude. Valid in 10 Mbits/s mode only. The default is 0. Autopolarity Function Enable. When this bit is a 1 and the LU6612 is in 10 Mbits/s mode, the autopolarity function will determine if the TP link is wired with a polarity reversal. If there is a polarity reversal, the LU6612 will assert the APS bit (register 28, bit 6) and correct the polarity reversal. If this bit is a 0 and the device is in 10 Mbits/s mode, the reversal will not be corrected. The default is 0. Reference Select. When this bit is a 1, the external 10 MHz reference of pin REF10 is used for phase alignment. This bit defaults to a 0. Serial Select. When this bit is set to a 1, 10 Mbits/s serial mode will be selected. When the LU6612 is in 100 Mbits/s mode, this bit will be ignored. The default is 0. No Link Partner Mode. Setting this bit to a 1 will allow 10 Mbits/s operation with link pulses disabled. If the LU6612 is configured for 100 Mbits/s operation, setting this bit will not affect operation. The default is 0.
30.3 (APF_EN)
R/W
30.2 (REF_SEL) 30.1 (SERIAL _SEL)
R/W R/W
30.0 (ENA_NO_LP)
R/W
1. Note that the format for the pin descriptions is as follows: the first number is the register number, the second number is the bit position in the register, and the name of the instantiated pad is in capital letters. 2. R = read, W = write.
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Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
MODE Selection
LU6612 can be forced to operate in specific operating modes. This is achieved by configuring the MODE pins to the appropriate values at powerup/reset. The strapping options of the MODE pins are latched on reset to set the default values of various registers. The values can be modified by writing into the registers. The MODE[2:0] pins have 100 k internal pull-ups. If MODE[2:0] are left floating, LU6612 will default to all capable, autonegotiation enabled mode. The different modes of operation of LU6612 and the register bits affected are presented in the following table. Table 20. Operation Modes of LU6612 MODE [2:0] 000 001 010 011 100 101 110 111 Definition 10Base-T, half-duplex with autonegotiation disabled 10Base-T, full-duplex with autonegotiation disabled 100Base-TX, half-duplex with autonegotiation disabled 100Base-TX, full-duplex with autonegotiation disabled Advertise 100Base-TX, half-duplex autonegotiation enabled Reserved Isolate MII All capable, autonegotiation enabled Register.Bit 0.8 0.10 0.12 0.13 4.5 0 1 0 1 0 -- 0 0 0 0 0 0 0 -- 1 0 0 0 0 0 1 -- 0 1 0 0 1 1 1 -- 1 1 1 1 0 0 0 -- 1 1 4.6 0 1 0 0 0 -- 1 1 4.8 1 1 1 1 0 -- 0 1
Table 21. LU6612 Crystal Specifications Parameter Type Frequency Stability Shunt Capacitor Load Capacitor Series Resistance Requirement Quartz Fundamental Mode 25 MHz 25 ppm, 0--70 C 7 pF 20 pF <30
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LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
Absolute Maximum Ratings (TA = 25 C)
Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Table 22. Absolute Maximum Ratings Parameter Ambient Operating Temperature Storage Temperature Voltage on Any Pin with Respect to Ground Maximum Supply Voltage Symbol TA Tstg -- -- Min 0 -40 -0.5 -- Max 70 125 VDD + 0.5 5.5 Unit C C V V
Table 23. Operating Conditions Parameter Operating Supply Voltage Power Dissipation: 100 Mbits/s TX 10 Mbits/s Autonegotiating Symbol -- PD PD PD Min 4.75 -- -- -- Typ* 5.0 1.4 1.0 1.0 Max 5.25 1.6 1.35 -- Unit V W W mW
* Typical power dissipations are specified at 5.0 V and 25 C. This is the power dissipated by the LU6612 transmitting over 100 meters of cable.
Electrical Characteristics
The following specifications apply for VDD = 5 V 5%. Table 24. dc Characteristics Parameter TTL Inputs: Input High Voltage Input Low Voltage Input High Current Input Low Current Input Leakage Current TTL Outputs: Output High Voltage Output Low Voltage Output Short-circuit Current 10 Mbits/s Twisted Pair: Input Voltage 100 Mbits/s Twisted Pair: Input Voltage 10 Mbits/s Twisted Pair: Output Current 100 Mbits/s Twisted Pair: Output Current Symbol VIH VIL IIH IIL IL VOH VOL ISC VDIFF VDIFF VDIFF VDIFF Min 2.0 -- -- -- -- 2.4 -- -15 0.35 -- 45 19 Typ -- -- -- -- -- -- -- -- -- -- 50 20 Max -- 0.8 50 -400 50 -- 0.45 -85 2.0 1.5 55 21 Unit V V A A A V V mA V V mA mA
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Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary)
Table 25. MII Management Interface Timing (25 pF Load) Name t1 t2 t3 t4 t5 t6 Parameter MDIO Valid to Rising Edge of MDC (setup) Rising Edge of MDC to MDIO Invalid (hold) MDC Falling Edge to MDIO Valid (prop. delay) MDC High* MDC Low* MDC Period* Min 10 10 0 -- 40 80 Typ -- -- -- 200 200 400 Max -- -- 40 -- -- -- Unit ns ns ns ns ns ns
* When operating MDC above 6.25 MHz, MDC must be synchronous with LSCLK and have a setup time of 15 ns and a hold time of 5 ns, with respect to LSCLK. MDC
MDIO t1 t2
5-4959(F).a
Figure 6. MDIO Input Timing
t6 MDC t5 MDIO t3
5-4960(F).c
t4
Figure 7. MDIO Output Timing
MDC

MDIO
5-5312(F).r1
Note: MDIO turnaround (TA) time is a 2-bit time spacing between the register address field, and the data field of a frame to avoid drive contention on MDIO during a read transaction. During a write to the LU6612, these bits are driven to a 10 by the station. During a read, the MDIO is not driven during the first bit time and is driven to a 0 by the LU6612 during the second bit time.
Figure 8. MDIO During TA (Turnaround) of a Read Transaction
Lucent Technologies Inc.
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LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
Timing Characteristics (Preliminary) (continued)
Table 26. MII Data Timing (25 pF Load) Name t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 Parameter RXD[3:0], RX_ER, RX_DV, Valid to RX_CLK High RX_CLK High to RXD[3:0], RX_DV, RX_ER Invalid RX_CLK High RX_CLK Low RX_CLK Period TX_CLK High TX_CLK Low TX_CLK Period TXD[3:0], TX_EN, TX_ER, Setup to TX_CLK TXD[3:0], TX_EN, TX_ER, Hold to TX_CLK TXD[3:0], TX_EN, TX_ER Setup to LSCLK* TXD[3:0], TX_EN, TX_ER, Hold to LSCLK* First Bit of J on RX/RY While Transmitting Data to COL Assert (half-duplex mode) First Bit of T Received on RX/RY While Transmitting to COL Deasserted (half-duplex mode) Min 10/100 10/100 14/180 14/180 -- 14/180 14/180 -- 15/140 0/0 10 0 -- -- Typ -- -- -- -- 40 -- -- 40 -- -- -- -- -- -- Max -- -- 26/220 26/220 -- 26/220 26/220 -- -- -- -- -- 170 210 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns
* 100 Mbits/s only.
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Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary) (continued)
t5 t4 RX_CLK t3
RXD[3:0] RX_DV RX_ER t1 t2 t8 TX_CLK t7 TXD[3:0] TX_EN TX_ER t6
t9 t10
LSCLK
TXD[3:0] TX_EN TX_ER t11 t12 1st BIT OF J RX/RY 1st BIT OF T
COL t13 t14
5-5432(F).cr1
Figure 9. MII Timing Requirements for LU6612
Lucent Technologies Inc.
27
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
Timing Characteristics (Preliminary) (continued)
Table 27. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK Name t15 t16 t17 t18 Parameter RX/RY Activity to CRS Assertion RX/RY Activity to RX_CLK Valid IDL to CRS Deassertion Dead Signal to CRS Deassertion Min 40 800 200 400 Max 500 2300 550 1000 Unit ns ns ns ns
(RECEIVE--DEAD SIGNAL) (NOT IDL) (RECEIVE--START OF PACKET) RX/RY (RECEIVE--END OF PACKET) IDL
CRS t15 RX_CLK t16
5-5293(F).mr1
t17
t18
Figure 10. Serial 10 Mbits/s Timing for RX/RY, CRS, and RX_CLK Table 28. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK Name t19 t20 t21 t22 t23 Parameter TX_EN Asserted to Transmit Pair Activity TX_EN Asserted to CRS Asserted Due to Internal Loopback TX_EN Asserted to RX_CLK Valid Due to Internal Loopback TX_EN Deasserted to IDL Transmission IDL Pulse Width Min 50 5 1000 50 250 Max 400 1900 1700 300 350 Unit ns ns ns ns ns
(TRANSMIT--START OF PACKET) TX_EN
(TRANSMIT--END OF PACKET)
TX/TY t19 CRS t22
IDL t23
t20 RX_CLK t21
5-5293(F).nr1
Figure 11. Serial 10 Mbits/s Timing for TX_EN, TX/TY, CRS, and RX_CLK 28 Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary) (continued)
Table 29. Serial 10 Mbits/s Timing for TX_EN, RX/RY, and COL Name t24 t25 t26 t27 t28 Parameter Time to Assert COL; LU6612 Is Transmitting; Receive Activity Starts Time to Deassert COL; LU6612 Is Transmitting; Receive Activity Ceases Time to Assert COL; LU6612 Is Receiving; Transmit Activity Starts Time to Deassert COL; LU6612 Is Receiving; Transmit Activity Ceases COL Pulse Width Min 40 300 5 5 100 Max 400 900 400 900 -- Unit ns ns ns ns ns
(TRANSMITTING--RECEIVE COLLISION DETECTED) TX_EN
(RECEIVING--TRANSMIT COLLISON DETECTED)
RX/RY
IDL
COL
t24
t25
t26 t28
t27
5-5293(F).l
Figure 12. Serial 10 Mbits/s Timing for TX_EN, RX/RY, and COL
Lucent Technologies Inc.
29
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
Timing Characteristics (Preliminary) (continued)
Table 30. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD (25 pF Load) Name t29 t30 t31 t32 t33 t34 t35 Parameter RXD Setup Before RX_CLK Rising Edge RXD Held Past RX_CLK Edge RX_CLK Low to CRS Deassertion (at end of received packet) TX_EN Setup Before TX_CLK Rising Edge TX_EN Held Past TX_CLK Rising Edge TXD Setup Before TX_CLK Rising Edge TXD Held Past TX_CLK Rising Edge Min 30 30 40 30 0 30 0 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns
RX_CLK
CRS t31 RXD t29 (START OF PACKET) t30 (END OF PACKET)
TX_CLK t32 TX_EN t34 TXD t35 t33
LAST BIT
5-2736(F).d
Figure 13. Serial 10 Mbits/s Timing for RX_CLK, CRS, RXD, TX_CLK, TX_EN, and TXD
30
Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary) (continued)
Table 31. Serial 10 Mbits/s Timing for RX_CLK and TX_CLK (25 pF Load) Name t36 t37 t38 t39 Parameter RX_CLK Low Pulse Width RX_CLK High Pulse Width TX_CLK Low Pulse Width TX_CLK High Pulse Width Min 45 45 45 45 Max 55 55 55 55 Unit ns ns ns ns
(TRANSMITTING--RECEIVE COLLISION DETECTED) TX_EN
(RECEIVING--TRANSMIT COLLISON DETECTED)
RX/RY
IDL
COL
t24
t25
t26 t28
t27
5-2737(F).dr1
Figure 14. Serial 10 Mbits/s Timing Diagram for RX_CLK and TX_CLK
Lucent Technologies Inc.
31
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
Timing Characteristics (Preliminary) (continued)
Table 32. 100 Mbits/s MII Transmit Timing Name t40 t41 t42 Parameter Rising Edge of TX_CLK Following TX_EN Assertion to CRS Assertion Rising Edge of TX_CLK Following TX_EN Assertion to TX/TY Rising Edge of TX_CLK Following TX_EN Deassertion to CRS Deassertion Min -- -- -- Max 40 60 40 Unit ns ns ns
TX_CLK
TX_EN
TXD[3:0] t40 CRS 1st BIT OF J t41 TX/TY 1st BIT OF T t42
5-3745(F).er1
Figure 15. 100 Mbits/s MII Transmit Timing
32
Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Timing Characteristics (Preliminary) (continued)
Table 33. 100 Mbits/s MII Receive Timing Name t43 t44 t45 t46 Parameter RX/RY 1st Bit of J Receive Activity to CRS Asserted RX/RY Receive Activity to Receive Data Valid RX/RY Receive Activity Cease (1st bit of T) to CRS Deasserted RX/RY Receive Activity Cease (1st bit of T) to Receive Data Not Valid Min -- -- -- -- Max 170 210 210 210 Unit ns ns ns ns
1st BIT OF J RX/RY t43 CRS
1st BIT OF T
t45
RX_CLK t44 RX_DV t46 RX_ER
RXD[3:0]
5-3747(F).er1
Figure 16. 100 Mbits/s MII Receive Timing
Lucent Technologies Inc.
33
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
Outline Diagram
64-Pin TQFP
Dimensions are in millimeters.
12.00 0.20 10.00 0.20 PIN #1 IDENTIFIER ZONE
64 49
1.00 REF
0.25 GAGE PLANE
1
48
SEATING PLANE 0.45/0.75
10.00 0.20 12.00 0.20
DETAIL A
16
33
0.106/0.200
17 32
0.19/0.27 DETAIL A DETAIL B 1.40 0.05 1.60 MAX SEATING PLANE 0.08 0.50 TYP 0.05/0.15 DETAIL B 0.08
M
5-3080r5
34
Lucent Technologies Inc.
Data Sheet July 2000
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Technical Document Types
The following descriptions pertain to the types of individual product data sheets. Data sheets provide a definition of the particular integrated circuit device by detailing its full electrical and physical specifications. They are intended to be the basic source of information for designers of new systems and to provide data for users requiring information on equipment troubleshooting, training, incoming inspection, equipment testing, and system design modification. A data sheet is classified according to the following criteria: Advance Data Sheet: An advance data sheet presents the device's proposed design architecture. It lists target specifications but may not have complete parameter values and is subject to change. Preliminary Data Sheet: Preliminary data sheets describe the characteristics of initial prototypes. Data Sheet: When a data sheet has the specifications of a product in full production and has complete parameter values, it is considered final and is classified as a data sheet.
Lucent Technologies Inc.
35
LU6612 FASTCAT Single-FET for 10Base-T/100Base-TX
Data Sheet July 2000
Ordering Information
Device Code LU6612-T64-DB Comcode 108160680 Package 64-Pin TQFP Temperature 0 C to 70 C
For additional information, contact your Microelectronics Group Account Manager or the following: http://www.lucent.com/micro INTERNET: docmaster@micro.lucent.com E-MAIL: N. AMERICA: Microelectronics Group, Lucent Technologies Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA PACIFIC: Microelectronics Group, Lucent Technologies Singapore Pte. Ltd., 77 Science Park Drive, #03-18 Cintech III, Singapore 118256 Tel. (65) 778 8833, FAX (65) 777 7495 CHINA: Microelectronics Group, Lucent Technologies (China) Co., Ltd., A-F2, 23/F, Zao Fong Universe Building, 1800 Zhong Shan Xi Road, Shanghai 200233 P R. China Tel. (86) 21 6440 0468, ext. 325, FAX (86) 21 6440 0652 . JAPAN: Microelectronics Group, Lucent Technologies Japan Ltd., 7-18, Higashi-Gotanda 2-chome, Shinagawa-ku, Tokyo 141, Japan Tel. (81) 3 5421 1600, FAX (81) 3 5421 1700 EUROPE: Data Requests: MICROELECTRONICS GROUP DATALINE: Tel. (44) 1189 324 299, FAX (44) 1189 328 148 Technical Inquiries: GERMANY: (49) 89 95086 0 (Munich), UNITED KINGDOM: (44) 1344 865 900 (Ascot), FRANCE: (33) 1 40 83 68 00 (Paris), SWEDEN: (46) 8 600 7070 (Stockholm), FINLAND: (358) 9 4354 2800 (Helsinki), ITALY: (39) 02 6608131 (Milan), SPAIN: (34) 1 807 1441 (Madrid)
Lucent Technologies Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information. FASTCAT is a trademark of Lucent Technologies Inc.
Copyright (c) 2000 Lucent Technologies Inc. All Rights Reserved
July 2000 DS00-355LAN (Replaces DS99-105LAN)

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